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SSTUM32865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
Rev. 01 -- 19 September 2007 Product data sheet
1. General description
The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUM32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. The SSTUM32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm x 13 mm of board space, allows for adequate signal routing and escape using conventional card technology.
2. Features
I 28-bit data register supporting DDR2 I Fully compliant to JEDEC standard for SSTUB32865 I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 x SSTUB32864 or 2 x SSTUB32866) I Parity checking function across 22 input data bits I Parity out signal I Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed I Meets or exceeds SSTUB32865 JEDEC standard speed performance I Supports up to 450 MHz clock frequency of operation I Permanently configured for high output drive I Optimized pinout for high-density DDR2 module design I Chip-selects minimize power consumption by gating data outputs from changing state I Two additional chip select inputs allow optional flexible enabling and disabling
NXP Semiconductors
SSTUM32865
1.8 V DDR2-800 registered buffer with parity
I I I I I
Supports Stub Series Terminated Logic SSTL_18 data inputs Differential clock (CK and CK) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 160-ball 9 mm x 13 mm, 0.65 mm ball pitch TFBGA package
3. Applications
I 400 MT/s to 800 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality
4. Ordering information
Table 1. Ordering information Solder process Package Name SSTUM32865ET/G SSTUM32865ET/S Description Version Type number
Pb-free (SnAgCu solder ball TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-2 compound) 160 balls; body 9 x 13 x 0.7 mm Pb-free (SnAgCu solder ball TFBGA160 plastic thin fine-pitch ball grid array package; SOT802-2 compound) 160 balls; body 9 x 13 x 0.7 mm
4.1 Ordering options
Table 2. Ordering options Topside mark SSTUM32865ET SSTUM32865ETS Temperature range Tamb = 0 C to +70 C Tamb = 0 C to +85 C Type number SSTUM32865ET/G SSTUM32865ET/S
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
5. Functional diagram
(CS ACTIVE) VREF DQ
22
PARIN
R
PARITY GENERATOR AND CHECKER
SSTUM32865
PTYERR
Q0A D0 DQ Q0B R Q21A D21 DQ Q21B R QCS0A DQ R QCS0B
DCS0
CSGATEEN DCS1 DCS2 DCS3 DCKE0, DCKE1
2
QCS1A DQ QCS1B R
DQ R
2
QCKE0A, QCKE1A QCKE0B, QCKE1B QODT0A, QODT1A QODT0B, QODT1B
DODT0, DODT1
2
DQ R
2
RESET CK CK
002aac647
Fig 1. Functional diagram of SSTUM32865
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUM32865ET/G SSTUM32865ET/S
2 1 A B C D E F G H J K L M N P R T U V
002aac648
ball A1 index area
4 3 5
6 7
8 9
10 12 11
Transparent top view
Fig 2. Pin configuration for TFBGA160
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
1 A B C D E F G H J K L M N P R T U V VREF D1 D3 D6 D7 D11 D18 CSGATEEN CK CK RESET D0 D17 D19 D13 DODT1 DCKE0 VREF
2 n.c. D2 D4 D5 D8 D9 D12 D15 DCS0 DCS1 D14 D10 D16 D21 D20 DODT0 DCKE1 MCL
3 PARIN n.c.
4 n.c. n.c.
5 n.c. n.c.
6 QCKE1A QCKE1B
7 QCKE0A QCKE0B
8 Q21A Q21B
9 Q19A Q19B
10 Q18A Q18B
11 Q17B QODT0B QODT1B
12 Q17A QODT0A QODT1A Q20A Q16A Q1A Q2A Q5A QCS0A QCS1A Q6A Q10A Q9A Q11A Q15A Q14A Q8B Q8A
002aac650
VDDL VDDL VDDL VDDL DCS2 GND DCS3 GND GND VDDL GND GND
GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL
n.c. VDDL
n.c. VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR
GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND
Q20B Q16B Q1B Q2B Q5B QCS0B QCS1B Q6B Q10B Q9B Q11B Q15B Q14B
VDDL VDDL
VDDR GND
VDDR GND
MCL MCL
PTYERR n.c.
MCH MCH
Q3B Q3A
Q12B Q12A
Q7B Q7A
Q4B Q4A
Q13B Q13A
Q0B Q0A
160-ball, 12 x 18 grid; top view. An empty cell indicates no ball is populated at that grid point. n.c. denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that must be connected LOW. MCH denotes a pin that must be connected HIGH.
Fig 3. Ball mapping
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
6.2 Pin description
Table 3. Symbol Ungated inputs DCKE0, DCKE1 DODT0, DODT1 D0 to D21 U1, U2 T2, T1 M1, B1, B2, C1, C2, D2, D1, SSTL_18 E1, E2, F2, M2, F1, G2, R1, L2, H2, N2, N1, G1, P1, R2, P2 J2, K2, H4, K4 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. SSTL_18 DRAM function pins not associated with Chip Select. Pin description Pin Type Description
Chip Select gated inputs
Chip Select inputs DCS0, DCS1, DCS2, DCS3[1] DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGATEEN = HIGH) when at least one Chip Select input is LOW. DCS2 and DCS3 are not re-driven and can be left open-circuit to default HIGH by means of its internal pull-up resistors. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.
Re-driven outputs Q0A to Q21A V11, F12, G12, V6, V9, H12, SSTL_18 L12, V8, V12, N12, M12, P12, V7, V10, T12, R12, E12, A12, A10, A9, D12, A8 U11, F11, G11, U6, U9, H11, L11, U8, U12, N11, M11, P11, U7, U10, T11, R11, E11, A11, B10, B9, D11, B8 J12, K12, J11, K11 A7, A6, B7, B6
Q0B to Q21B
QCS0A, QDS1A, QCS0B, QCS1B QCKE0A, QCKE1A, QCKE0B, QCKE1B
QODT0A, QODT1A, B12, C12, B11, C11 QODT0B, QODT1B Parity input PARIN Parity error PTYERR U4 open-drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). A3 SSTL_18 Parity input for the D0 to D21 inputs. Arrives one clock cycle after the corresponding data input.
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
Table 3. Symbol
Pin description ...continued Pin H1 Type 1.8 V LVCMOS with weak pull-up Description Chip Select Gate Enable. When HIGH, the D0 to D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0 to D21 inputs will be latched and redriven on every rising edge of the clock. Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Must be connected to a logic LOW. Must be connected to a logic HIGH. 1.8 V LVCMOS with weak pull-up 0.9 V nominal Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. Power supply voltage. Power supply voltage. Ground.
Program inputs CSGATEEN
Clock inputs CK, CK J1, K1 SSTL_18
Miscellaneous inputs MCL MCH RESET U3, V2, V3 U5, V5 L1
VREF VDDL VDDR GND
A1, V1 D4, E4, E6, F4, G4, K5, N4, N5, P5, P6, R5, R6 E7, F8, F9, G8, G9, J8, J9, L8, L9, N8, N9, P7, P8 D5, D8, D9, E5, E8, E9, F5, G5, H5, H8, H9, J4, J5, K8, K9, L4, L5, M4, M5, M8, M9, P4, P9, R4, R7, R8, R9 A2, A4, A5, B3, B4, B5, D6, D7, V4
n.c.
Ball present but not connected to die.
[1]
If application does not require DCS2 and DCS3, it is allowed to connect H4 and K4 to VDD.
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
7. Functional description
7.1 Function table
Table 4. RESET H H H H H H H H H H H H H H H L Function table (each flip-flop) Inputs DCS0[2] DCS1[2] L L L L L L H H H H H H H H H X or floating L L L H H H L L L H H H H H H X or floating CSGATEEN X X X X X X X X X L L L H H H X or floating CK L or H L or H L or H L or H L or H X or floating CK L or H L or H L or H L or H L or H X or floating Dn, DODTn, DCKEn L H X L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs[1] QCS0 L L Q0 L L Q0 H H Q0 H H Q0 H H Q0 L QCS1 L L Q0 H H Q0 L L Q0 H H Q0 H H Q0 L QODTn, QCKEn L H Q0 L H Q0 L H Q0 L H Q0 L H Q0 L
[1] [2]
Q0 is the previous state of the associated output. DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
Table 5. RESET H H H H H H H H H H L
Parity and standby function table Inputs DCS0[1] L L L L H H H H H X X or floating DCS1[1] H H H H L L L L H X X or floating CK L or H X or floating CK L or H X or floating of inputs = H (D0 to D21) even odd even odd even odd even odd X X X or floating PARIN[2] L L H H L L H H X X X or floating Output PTYERR[3][4] H L L H H L L H PTYERR0 PTYERR0 H
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
[1] [2] [3] [4]
DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated correctly. This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is `don't care' for PTYERR. PTYERR0 is the previous state of output PTYERR.
7.2 Functional information
This 28-bit 1 : 2 registered buffer with parity is designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUM32865 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUM32865 ensures that the outputs remain LOW, thus ensuring no glitches on the output. The device monitors DCS0, DCS1, DCS2 and DCS3 inputs and will gate the Qn outputs from changing states when all DCSn inputs are HIGH. If DCSn input is LOW, the Qn outputs will function normally. The RESET input has priority over the DCSn control and will force the Qn outputs LOW and the PTYERR output HIGH. If the DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to ground, in which case, the set-up time requirement for DCSn would be the same as for the other Dn data inputs. The SSTUM32865 includes a parity checking function. The SSTUM32865 accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTUM32865 for its basic register functionality, signal definition and performance is based upon the industry-standard SSTU32864, but provides key operational features which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3, CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or more of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the clock. The 22 `Chip-Select-gated' input signals associated with this function include addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they are independent of CS. The CS gating function can be disabled by tying CSGATEEN LOW, enabling all internal latches to be updated on every rising edge of the clock.
Table 6. Mode Gating Non-gating Chip Select gating mode Signal name CSGATEEN HIGH CSGATEEN LOW Description Registers only re-drive signals to the DRAMs when Chip Select inputs are LOW. Registers always re-drive signals on every clock cycle, independent of the state of the Chip Select inputs.
7.3.2 Parity error checking and reporting
The SSTUM32865 incorporates a parity function, whereby the signal received on input pin PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs. The received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. The 22 CS-gated input signals will be latched and re-driven on the first clock, and any error will be reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a common signal pin for reporting the occurrence of a parity error during a valid command cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive clock cycles to allow the memory controller sufficient time to sense and capture the error even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all internal latches and all outputs will be driven LOW quickly except the PTYERR output, which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequence
The reset function for the SSTUM32865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles.
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
RESET
DCSn
m CK
m+1
m+2
m+3
m+4
CK tACT Dn (1) tPDM, tPDMSS CK to Q Qn
tsu
th
tsu PARIN tPHL CK to PTYERR PTYERR
th
tPHL, tPLH CK to PTYERR
002aaa983
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of tACT(max) to avoid false error.
Fig 4. RESET switches from LOW to HIGH
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
RESET
DCSn
m CK
m+1
m+2
m+3
m+4
CK tsu th
Dn (1) tPDM, tPDMSS CK to Q Qn tsu
th
PARIN tPHL, tPLH CK to PTYERR PTYERR
Unknown input event
Output signal is dependent on the prior unknown event
002aaa984
HIGH or LOW
Fig 5. RESET being held HIGH
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
RESET
tINACT
DCSn
CK (1)
CK (1)
Dn (1) tPHL RESET to Q Qn
PARIN (1) tPLH RESET to PTYERR PTYERR
002aac649
HIGH, LOW, or Don't care
HIGH or LOW
(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of tINACT(max).
Fig 6. RESET switches from HIGH to LOW
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
Dn
22
DQ
22
QnA
QnB
D
D
LATCHING AND RESET FUNCTION(1)
PTYERR
PARIN
D
CLOCK
002aaa417
(1) This function holds the error for two cycles. For details, see Section 7 "Functional description" and Figure 4 "RESET switches from LOW to HIGH".
Fig 7. Parity logic diagram
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
8. Limiting values
Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO IDDC Tstg Vesd Parameter supply voltage input voltage output voltage input clamping current output clamping current output current continuous current through each VDD[2] or GND pin storage temperature electrostatic discharge voltage Human Body Model (HBM); 1.5 k; 100 pF Machine Model (MM); 0 ; 200 pF receiver driver VI < 0 V or VI > VDD VO < 0 V or VO > VDD continuous; 0 V < VO < VDD
[1] [1]
Conditions
Min -0.5 -0.5 -0.5 -65 2 150
Max +2.5 +2.5 VDD + 0.5 -50 50 50 100 +150 -
Unit V V V mA mA mA mA C kV V
[1] [2]
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. Pins VDDL or VDDR.
9. Recommended operating conditions
Table 8. Symbol VDD Vref VT VI VIH(AC) VIL(AC) VIH(DC) VIL(DC) VIH VIL VICR VID IOH IOL Tamb Recommended operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage common mode input voltage range differential input voltage HIGH-level output current LOW-level output current ambient temperature operating in free air SSTUM32865ET/G SSTUM32865ET/S
[1] [2] The differential inputs must not be floating, unless RESET is LOW. The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.
(c) NXP B.V. 2007. All rights reserved.
Conditions
Min 1.7 0.49 x VDD Vref - 0.040 0
Typ 0.50 x VDD Vref -
Max 2.0 0.51 x VDD Vref + 0.040 VDD Vref - 0.250 Vref - 0.125 0.35 x VDD 1.125 -8 8 +70 +85
Unit V V V V V V V V V V V mV mA mA C C
data inputs (Dn) data inputs (Dn) data inputs (Dn) data inputs (Dn) RESET RESET CK, CK CK, CK
[1] [1] [1] [1] [2] [2]
Vref + 0.250 Vref + 0.125 0.65 x VDD 0.675 600 0 0
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1.8 V DDR2-800 registered buffer with parity
10. Characteristics
Table 9. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current supply current Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 2.0 V static standby current; RESET = GND; VDD = 2.0 V static operating current; RESET = VDD; VDD = 2.0 V; VI = VIH(AC) or VIL(AC) IDDD dynamic operating current per MHz clock only; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V per each data input; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V Ci input capacitance data inputs; VI = Vref 250 mV; VDD = 1.8 V CK and CK; VICR = 0.9 V; VID = 600 mV; VDD = 1.8 V RESET; VI = VDD or GND; VDD = 1.8 V Zo output impedance instantaneous steady-state
[1] Instantaneous is defined as within < 2 ns following the output data transition edge.
[1]
Min 1.2 -
Typ -
Max 0.5 5 2 40
Unit V V A mA mA
-
16
-
A
-
19
-
A
2.5 2 3 -
7 53
3.5 3 5 -
pF pF pF
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1.8 V DDR2-800 registered buffer with parity
Table 10. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol fclock tW tACT tINACT tsu Parameter clock frequency pulse width differential inputs active time differential inputs inactive time set-up time Chip Select; DCS0, DCS1 valid before clock switching Data; Dn valid before clock switching PARIN; PARIN before CK and CK th hold time input to remain valid after clock switching PARIN after CK and CK
[1] [2] [3] This parameter is not necessarily production tested. Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Conditions CK, CK HIGH or LOW
[1][2] [1][3]
Min 1 0.6
Typ -
Max 450 10 15 -
Unit MHz ns ns ns ns
0.5 0.5 0.4 0.4
-
-
ns ns ns ns
Table 11. Switching characteristics Over recommended operating conditions, unless otherwise noted. Symbol fmax tPDM tLH tHL tPLH tPDMSS tPHL
[1] [2]
Parameter maximum input clock frequency peak propagation delay LOW to HIGH delay time HIGH to LOW delay time LOW-to-HIGH propagation delay simultaneous switching peak propagation delay HIGH-to-LOW propagation delay
Conditions CK and CK to output CK and CK to PTYERR CK and CK to PTYERR from RESET to PTYERR CK and CK to output RESET to output
[1][2] [1]
Min 450 1.0 1.2 1 -
Typ -
Max 1.4 3 3 3 1.5 3
Unit MHz ns ns ns ns ns ns
Includes 350 ps of test-load transmission line delay. This parameter is not necessarily production tested.
Table 12. Output edge rates Over recommended operating conditions, unless otherwise noted. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate absolute difference between dV/dt_r and dV/dt_f Conditions Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
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1.8 V DDR2-800 registered buffer with parity
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT
50
CK inputs
CK CK test point
RL = 100
delay = 350 ps Zo = 50
RL = 1000
OUT
CL = 30 pF(1) RL = 1000
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 8. Load circuit
LVCMOS RESET 0.5VDD tINACT IDD(1) 0.5VDD
VDD 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 9. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 10. Voltage waveforms; pulse duration
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Product data sheet
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1.8 V DDR2-800 registered buffer with parity
CK VICR CK tsu input Vref th VIH Vref VIL
002aaa374
VID
VID = 600 mV. Vref = 0.5VDD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; set-up and hold times
CK VICR CK tPLH tPHL VOH output VT VOL 002aaa375 VICR Vi(p-p)
tPLH and tPHL are the same as tPD.
Fig 12. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET 0.5VDD VIL tPHL VOH output VT VOL 002aaa376
tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; propagation delay times (reset to output)
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Product data sheet
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1.8 V DDR2-800 registered buffer with parity
11.2 Output slew rate measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement
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Product data sheet
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11.3 Error output load circuit and voltage measurement
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 1 k
OUT
CL = 10 pF(1)
test point
002aaa500
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, error output measurements
LVCMOS RESET 0.5VDD
VDD
0V tPLH VOH output waveform 2 0.15 V
0V
002aaa501
Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input
timing inputs
VICR tHL
VICR
Vi(p-p)
VDD output waveform 1 0.5VDD
002aaa502
VOL
Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
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Product data sheet
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
timing inputs
VICR tLH
VICR
Vi(p-p)
VOH output waveform 2 0.15 V
002aaa503
0V
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
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Product data sheet
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1.8 V DDR2-800 registered buffer with parity
12. Package outline
TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.7 mm
D B A
SOT802-2
ball A1 index area
E
A
A2 A1
detail X
e1 1/2 e e b v w
M M
C CAB C y1 C y
V U T R P N M L K J H G F E D C B A
e e2 1/2 e
ball A1 index area
1
2
3
4
5
6
7
8
9
10
11
12
X 5 scale 10 mm
0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.15 A1 0.35 0.25 A2 0.80 0.65 b 0.45 0.35 D 9.1 8.9 E 13.1 12.9 e 0.65 e1 7.15
e2 11.05
v 0.15
w 0.08
y 0.1
y1 0.1
OUTLINE VERSION SOT802-2
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-06-21 05-07-13
Fig 22. Package outline SOT802-2 (TFBGA160)
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Product data sheet
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1.8 V DDR2-800 registered buffer with parity
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
Rev. 01 -- 19 September 2007
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NXP Semiconductors
SSTUM32865
1.8 V DDR2-800 registered buffer with parity
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14
Table 13. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 14. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23.
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Product data sheet
Rev. 01 -- 19 September 2007
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1.8 V DDR2-800 registered buffer with parity
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 15. Acronym CMOS DDR2 DIMM DRAM LVCMOS MT/s RDIMM SSTL SSTL_18 Abbreviations Description Complementary Metal Oxide Semiconductor Double Data Rate 2 Dual In-line Memory Module Dynamic Random Access Memory Low Voltage Complementary Metal Oxide Semiconductor Mega Transfers per second Registered Dual In-line Memory Module Stub Series Terminated Logic Stub Series Terminated Logic for 1.8 V
15. Revision history
Table 16. Revision history Release date 20070919 Data sheet status Product data sheet Change notice Supersedes Document ID SSTUM32865_1
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Product data sheet
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SSTUM32865
1.8 V DDR2-800 registered buffer with parity
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
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1.8 V DDR2-800 registered buffer with parity
18. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 8 9 10 11 11.1 11.2 11.3 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 8 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional information . . . . . . . . . . . . . . . . . . . 9 Functional differences to SSTU32864 . . . . . . 10 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3, CSGATEEN) . . . . . . . . 10 Parity error checking and reporting. . . . . . . . . 10 Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up sequence . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended operating conditions. . . . . . . 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output slew rate measurement. . . . . . . . . . . . 20 Error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Introduction to soldering . . . . . . . . . . . . . . . . . 24 Wave and reflow soldering . . . . . . . . . . . . . . . 24 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 September 2007 Document identifier: SSTUM32865_1

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